This article briefly introduces the structure and technical characteristics of ARM series processing, compares ARM7 and ARM9, further introduces the structure and characteristics of ARM9, and finally builds an IP voice gateway using ARM9E-S and uC/OS-II operating system Design.
With the rapid development of IP telephony technology, the implementation method of IP telephony is transitioning from PC To PC to Phone To Phone. In the Phone To Phone implementation method, an IP telephony gateway is needed to connect the PSTN and the Internet. Therefore, IP telephony gateway has become one of the hot topics in current research in the field of computers and communications. Nowadays, each company uses many methods to research and implement IP telephony gateway, but they all use their own hardware processing. Compared with other processors, ARM has the characteristics of micro size, low consumption, low cost, strong functions, and has a 16/32-bit dual instruction set. Because of its outstanding functions, ARM is the preferred processor in various fields. The combination of ARM processor and voice gateway has also become a new research field.
ARM cores are divided into categories such as ARM7, ARM9, ARM10 and StrongARM. Each category can be divided into categories.
Due to different user requirements, four internal performance modules can be selected to correspond to production. These four modules are represented by T, D, M and I respectively. T: means Thumb, the set of sixteen-bit instructions is expanded to thirty-two. D: means Debug. This kernel adopts a testable mode for easy setup and debugging. M: stands for Multiplier, which is an 8-bit magic weapon. I: stands for Embedded ICE Logic, which facilitates the implementation of logic circuits.
The ARM7 mode is ARMV4T three-level pipeline; the ARM9 mode is ARMV4T five-level pipeline; the ARM10 mode is ARMV5T six-level pipeline; ARM1020T uses ARM1OTDMI 32KI&D Caches MMU structure, 30OMHz clock, power consumption is 1W (2.OV power supply) or 00mW (1.5 V powered), can be used in a variety of commercial operating systems. The StrongARM processor adopts the five-level pipeline structure of ARMV4T.
ARM cores are divided into categories such as ARM7, ARM9, ARM10 and StrongARM. Each category can be divided into categories.
Due to different user requirements, four internal performance modules can be selected to correspond to production. These four modules are represented by T, D, M and I respectively. T: means Thumb, the set of sixteen-bit instructions is expanded to thirty-two. D: means Debug. This kernel adopts a testable mode for easy setup and debugging. M: stands for Multiplier, which is an 8-bit magic weapon. I: stands for Embedded ICE Logic, which facilitates the implementation of logic circuits.
The ARM7 mode is ARMV4T three-level pipeline; the ARM9 mode is ARMV4T five-level pipeline; the ARM10 mode is ARMV5T six-level pipeline; ARM1020T uses ARM1OTDMI 32KI&D Caches MMU structure, 30OMHz clock, power consumption is 1W (2.OV power supply) or 00mW (1.5 V powered), can be used in a variety of commercial operating systems. The StrongARM processor adopts the five-level pipeline structure of ARMV4T.
ARM9 adopts a new method for implementation, using intensive transistors
These are more than three times higher than ARM7 processors. Increasing the clock frequency and reducing the instruction execution cycle can achieve the above effects. The ARM7 processor uses a 3-stage pipeline, while the ARM9 uses a 5-stage pipeline. Higher-level implementations increase clock frequency and improve parallel processing. Under the same processing technology, the clock frequency of the ARM9TDMI processor is 1.8~2.2 times that of the ARM7TDMI.
The increase in processor power is attributed to the improvement of the instruction cycle. The superposition of instructions leads to an increase in the size of the capabilities, and this is still the case in the code. Top-level languages can improve abilities by more than 30%. The most significant improvement in instruction cycle time is the two LOADS and STORES. The running time of this code has been reduced by more than 30% from ARM7 to .ARM9. Because the internal structure of the first two PROCESSORs is different, the cycle time is reduced.Pasarela industrial
(1) The code and input and output ports of ARM9 are separate, allowing the PROCESSOR to extract instructions and read and write codes together. But ARM7 only has input and output ports, and it needs to fetch instructions and read and write code at the same time.
(2) The fifth-level assembly line brings a separate memory device and output to the assembly line, which can read the memory device and enter the output data into the temporary storage area.
The above two aspects design a continuous repetition time to complete the LOADS and STORES operation codes.