This paper introduces the internal data transmission architecture of the regional stability control device, and introduces the corresponding measures taken in each link from the perspective of improving the reliability of data transmission, mainly including the improved design of dual-port RAM related programs on the GPS interface board, and the analog data acquisition board On the application of FIFO, the use of complex programmable logic devices (CPLD) to implement data acquisition logic control and cyclic redundancy check (CRC), as well as the design of the ARCnet network application layer network communication protocol. These measures are simple in principle and easy to implement, and theoretical analysis and targeted experiments show that they can effectively improve the reliability of data transmission.
The regional stability control device can effectively improve the stability limit of the system by exchanging information between different nodes of the power system and taking corresponding control measures at different locations according to the operation mode and fault conditions of the entire network. The device was put into operation in three substations and two power plants of the eastern Heilongjiang power grid in March 1997. Without major changes in the grid structure, it ensured the long-term safe operation of the eastern power grid under high stability limits and alleviated The power shortage problem of the eastern power plant.
During the long-term operation of the device, it can be seen from the data recording files of the host computer that the reliability of data transmission within the device needs to be further improved. This is mainly manifested in: ① The data packets uploaded by the lower computer are lost; ② There is obviously bad data in some data packets (the deviation from the actual value is too large). Data transmission reliability is an important part of the overall working reliability of the stability control device. In some extreme cases, long-term (such as more than 10 consecutive cycles) data message loss or mistransmission will cause the device to misjudge the current power grid status, and even cause malfunction.
This article starts from the internal data transmission architecture of the regional stability control device, analyzes possible problems in each link of data transmission, and proposes and implements a series of corresponding measures to address these problems.
Data transmission system
The regional stability control device has a hierarchical structure of upper and lower computers to facilitate flexible configuration and meet the requirements of various applications. Network communication between the upper and lower computers is realized through the ARCnet network card. The lower computer is an industrial STD bus with a master-slave CPU structure. Only the master processor V40 can control the bus and access bus resources. The slave processor cannot directly access bus resources.The processors can be thought of as intelligent I/O on the bus, they only perform
Some specific functions do not participate in system-level decisions.
The internal data transmission system of the regional stability control device is shown in Figure 1. The transmission link where the analog and switching data collected by each plug-in card of the slave computer is sent to the memory of the host computer mainly includes: ① The main control processor V40 board and the GPS interface board exchange status and time information through dual-port RAM; ② V40 The board obtains the collected analog and digital data from the A/D conversion board and switch input board through the I/O port response method; ⑧The communication between the upper and lower computers is realized by the industrial token network ARCnet.
2 GPS interface board data transmission
The data exchanged between the main control processor V40 board and the microcontroller on the GPS interface board mainly includes: ① Useful time and status information extracted from the GPS receiver communication messages. This information is added as time tags to the analog quantities obtained through synchronous collection. and switch data messages; ② command and status bytes to ensure coordinated operation of the master-slave CPU structure.
The data exchange between the master and slave CPUs is frequent and the timing is complex and changeable. The DS1609 dual-port RAM of Dallas Company is selected as the data buffer and memory. The GPS interface board can indirectly participate in the system-level decision-making of the lower computer through the dual-port RAM method. DS1609 hardware design
It is simple and easy to implement, but the requirements for related software programming are relatively high. This is because it allows both ends to access the memory unit at the same time, but the chip itself does not provide hardware access conflict arbitration logic. Potential access conflicts must be avoided through software design methods. Otherwise, it may cause read/write contention and write/write contention conflicts for the same address, causing data misreading, data content uncertainty and other problems. Reflected in the GPS interface board, this access conflict will directly cause the main control processor V40 board to obtain erroneous data, causing the phenomenon of “pseudo loss” of data packets, that is, the data packet has actually been uploaded to the host computer, but due to the error in the header flag bit It cannot be recognized by the host computer, making the data unable to be effectively utilized.
The improved GPS interface board uses the “mailbox method” idea and combines the actual data traffic and flow direction to design dual-port RAM related programs. The main design ideas of the “mailbox method” are: ① The mailbox itself can ensure that there are no read/write conflicts and write/write conflicts. This can be achieved by querying the contents of a pair of mailbox flag memories. In special cases, it can also be implemented by a single memory; ② The mailbox is A sign of the read and write status on both sides of the storage section. This information can be used to avoid various possible conflicts.
When using the “mailbox method” to design a dual-port RAM program, attention should be paid; ① Before obtaining the write operation permission of a certain storage unit, the corresponding mailbox should be queried, and the write operation right should be released immediately after completing the write operation of a certain storage unit; ② The default dual-port RAM A certain side has a higher priority to obtain the write operation right. The side with a lower priority needs to query the flag memory ⒉ times in the process of obtaining the write operation right (the 2 query delays are determined according to the actual speed of the master and slave CPUs) to ensure In any case, only one side can obtain write operation rights for the same storage section at the same time.
The advantages of using the “mailbox method” to design a dual-port RAM program are: ① Even if the timing of related programs on both sides of the dual-port RAM is not carefully considered, it can ensure that read/write conflicts and write/write conflicts will not occur, which is especially suitable for communications Frequent and complex timing systems; ② Reduce the correlation of programs on both sides of the dual-port RAM, facilitate the structuring and modularization of program design, and improve the maintainability and inheritability of the program.
3A/D conversion board data transmission
The original A/D conversion board uses a single-chip microcomputer and dual-port RAM to realize the functions of data acquisition and data exchange with the lower computer system. Single-chip microcomputer and dual-port RAM systems involve a large number of chips, and their power consumption and heat generation are large. Poor heat dissipation will affect the stability of the circuit operation. Like the GPS interface board, the related programming of dual-port RAM requires consideration of many factors. When some strong electromagnetic interference occurs in an industrial site, data transmission will be affected, resulting in a large amount of bad data appearing instantly. At this time, the horizontal parity check used by the original A/D conversion board cannot detect an even number of errors and cannot meet the requirements.
It can be seen from the analysis that the system’s control signal to the A/D conversion board is to start sampling. This signal is provided by the network-wide synchronous sampling pulse sent by the GPS interface board and is implemented purely in hardware.In this way, the data transmitted by the A/D conversion board through the bus are all sent in one direction, mainly including analog quantities.
Data and its check code group and on-board status information (such as FIFO status, A/D conversion board data ready status, etc.). Noting the single data transmission direction and fixed data output sequence of this board, and considering the amount of data that needs to be buffered, IDT’s IDT7201 asynchronous FIFO was selected to replace the original dual-port RAM. The data read and write operations of FIFO can only be performed sequentially. The read and write operations only require the /W and /R signals to participate in the control and have nothing to do with the address signal, so the interface circuit is simple; at the same time, the hardware characteristics of the FIFO ensure that it is impossible to occur during use. In case of read-write conflicts, the reliability is high, and the related programming is simple and easy to implement.
The control logic of the A/D conversion board is implemented by a complex programmable logic device (CPLD), and the MAX7000 series chip of ALTERA Company is selected to replace the original single-chip microcomputer system. The advantages of MAX7000 are: ① Its programming is carried out by modifying logic function modules with fixed interconnection circuits, so the maximum delay between its input and output is predictable; ② Its logic block interconnection is lumped and has a higher operating frequency; ③High integration level, suitable for implementing more complex state machines and control circuits.
The state diagram of the A/D conversion board CPLD is shown in Figure 2. The control logic implemented by CPLD mainly includes: ① A/D conversion, such as starting conversion, switching channels, waiting for data, storing data, etc.; ② On-board status information display, such as FIFO status, trunk state machine progress, a set of data sampling end flags, etc. , This ensures that the main control processor V40 board can obtain sampling data in real time and accurately; ③ Implement cyclic redundancy check (CRC) on a set of collected data.
As can be seen from Figure 1, a large amount of analog data needs to go through the STD bus, the lower computer ARCnet network card and the upper computer network card before it can finally be sent to the upper computer memory for use. Obtaining analog data synchronized across the entire network is a key part of data transmission. Ring, in order to ensure the high reliability of the analog data in the process of being sent from the A/D conversion board to the host computer, it is necessary to perform error checking on the data packets. When it is found that there is a sudden error in the data received by the host computer, the use of this set of data will be abandoned to improve the reliability of data transmission.
The A/D conversion board initially uses horizontal parity check, that is, parity check is performed on the same bit of each character in the same data group, and finally a check word is obtained.This error detection scheme is simple and easy to implement, but when an even number of burst errors occur in the corresponding bits for XOR, this scheme
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