In view of the characteristics of high-energy X-ray industrial CT, a data transmission system based on USB2.0 was developed. The transmission system mainly includes the USB2.0 interface part and the transmission control part. The USB2.0 interface part uses Cypress’s EZ-USBFX2 series CY7C68013A chip, which is configured as a slave FIFO interface mode and transmits data to the host through block transmission. machine. The transmission control part uses Altera’s Cyclone series EP1C6Q240C8N chip to define a buffer to receive data from the detection part, generate logical control signals and timing signals, and send data to the USB endpoint buffer. Tests show that the transmission system is easy to expand, takes up less system resources, has a high transmission rate, and meets the requirements for high-energy X-ray industrial CT data transmission.
High-energy X-ray industrial CT generally uses electron linear accelerators above 2MeV as the ray source. The function of its data transmission system is to convert, collect, process and store the signals obtained by the detector for later image reconstruction. It is a high-energy X-ray industrial CT. key components. In high-energy X-ray industrial CT, the number of detectors is relatively large, and the characteristics of real-time scanning require that the data transmission system must have the characteristics of large capacity, high speed and high reliability. For the industrial CT data transmission system, the literature [1] uses the RS232 bus for data transmission with the host computer; the literature [2] designs a data transmission system based on the AT bus; the literature [3-4] uses the data collection and control system based on the PCI bus. Transmission system; Document [5] uses USB1.1 bus technology to realize data transmission, improves transmission performance and reduces development costs; Document [6] proposes an industrial CT data acquisition and transmission based on Nios II processor and USB interface This solution can transmit the measurement data in the 64 channels of the acquisition module to the PC in real time. It can be seen from this that industrial CT data transmission systems generally use ISA and PCI buses, and currently PCI is the main one. The maximum transmission rate of the ISA bus is 8.33 Mbps. The low transmission rate can easily cause transmission bottlenecks. Although the PCI bus transmission speed reaches 133 Mbps, it has shortcomings such as troublesome on-site installation, cumbersome wiring, high price, poor scalability, and difficulty in electromagnetic radiation shielding. The USB bus has the advantages of plug-and-play, easy expansion (can connect up to 127 external devices), low system resource usage (only one IRP), no bus competition, and high transmission rate (USB2.0 protocol transmission rate 480 Mbps). [7-8], therefore, introducing USB bus technology into high-energy industrial CT can effectively solve the shortcomings of transmission systems based on ISA and PCI bus.
1 System structure The USB interface chip of this transmission system adopts CY7C68013A (hereinafter referred to as FX2) in the EZ-USBFX2 series chips of Cypress Company. Its chip firmware is stored on the host instead of inside the chip. Code upgrades are easy. Mainly includes USB2.0 transceiver, serial interface engine (SIE), enhanced 8051, 16KB RAM, 4KB FIFO memory, I/O interface, data bus, address bus and general programmable interface (GP) IF)[9] . The transmission system adopts the SlaveFIFO method mainly based on FX2, and completes data transmission under the control of FPGA. The FPGA chip adopts EP1C6Q240C8N from Altera’s Cyclone series. The system composition is shown in Figure 1.
Figure 2 is the hardware connection diagram between FX2 and FPGA. In the figure, IFCLK is used to output the clock signal of the internal clock source, and FLAGA-FLAGD is used to report different FIFO states, indicating the status of “FIFO full” or “FIFO empty”. These pins are related to F The I/O terminal of PGA is connected by FPGA determines the level of the pin and decides when to read or write data to the FIFO; SLOE is used as an output enable to control the output of the FIFO data terminal; SLRD is the FIFO reading data control terminal, controlled by the FPG A outputs high and low levels to control data Read; SLWR is the FIFO write data control end, and the FP-GA outputs high and low levels to control the writing of data; FD[15:0] is the FIFO data bus, and its bit width can be 8 bits or 16 bits. The transmission system uses 16 bits, which is determined by the firmware program; FIFOADR[1:0] is the chip’s choice of which endpoint buffer to put on the FD bus.